Semiconductor processing is a well established technology for making microelectronic devices. This technology involves depositing thin films of insulator (dielectric) and metallic materials on the surface of semiconductor wafer. These films vary in thickness from a few Angstroms to a few microns depending on what function they serve in the structure of an electronic device. The device is built layer by layer starting from the surface of the semiconductor. The transistors, which are the active part of the device, are formed in the semiconductor and film stacks consisting of alternating metal-dielectric structures are built on top of the semiconductor. These thin films are etched at specific lithographically defined locations to form vias or contact holes. These vias or contacts are filled with conducting materials such as metals so that connections can be made from upper layer interconnects to lower layer interconnects. Interconnects connect different points of the device to each other within one plane.
There are tight tolerances for film thicknesses and lateral dimensions of the structures involved. Any deviation or excursion from a set of predefined design rules can be a serious yield limiting issue in the manufacturing of these devices. For example, if the thickness of a given layer deviates from the required specification, there would be a severe penalty on yield—a wrong film thickness is therefore a yield limiting deviation or defect. These issues have only become more important as integrated circuit processing technology advances to allow smaller device geometries. For this reason, film characterization has proven to be an important part of monitoring the yield and the operation of the device. Current technologies for film characterization include spectroscopic ellipsometry and reflectometry. Both these techniques rely on reflection of light from planar interfaces and they take advantage of changes in Fresnel reflectivity with wavelength and angle of illumination and their application to semiconductor processing is covered under U.S. Pat. Nos. 4,999,014; 5,042,951; 5,181,080; 5,329,357; 5,412,473; 5,596,411; 5,608,526; 5,771,094; 5,747,813; 5,917,594; and 6,323,946. It is important to note that for film characterization, reflectometry and ellipsometry rely on reflection of light from two-dimensional (2D) planes of film interfaces. Recently, a technology called scatterometry, covered under U.S. Pat. Nos. 6,429,943, 6,433,878, 6,483,580, 6,451,621 has emerged which can use the same hardware as an ellipsometer or a reflectometer for dimensional measurements. For example with these techniques the smallest dimension (critical dimension) printed, may be measured. As the world of microelectronics is moving toward nanotechnology, both critical dimension (CD) metrology and film thickness measurement are playing an increasingly vital role in high performance device fabrication. The devices of the future will require an increasing numbers of lithography masking steps, thereby increasing and accelerating the number of corresponding CD and film measurement steps.
Many structures, and their corresponding yield limiting deviations and defects are, in general, three-dimensional (3D). This is true for both the at the transistor level and also at the subsequent metal layers. At the transistor level one would be interested in measuring the sidewall angle, height, and profile of a feature with minimum dimensions. A wrong CD, profile, or sidewall angle would also be a yield limiting deviation or defect.
For interconnects, recently, the copper Damascene process has become the preferred technology. In this technology a layer of diffusion barrier material such as TaN is deposited on the walls of the trench and via. This process step is followed by depositing a seed layer of copper on top of the barrier layer. And finally through electroplating a thicker layer of copper fills up the trenches and vias. This process then is followed by the Chemical Mechanical Planarization (CMP). FIGS. 1A-B show the top and side views, respectively, of this structure after CMP. FIG. 1A shows the copper lines, the diffusion barrier layer and the inter-metal dielectric (IMD) layer separating the conductor lines from each other. In FIG. 1B, the side view additionally shows the trench etch stop, interlayer dielectric (ILD) and the dielectric diffusion barrier and the via for making connection to the lower layer. In FIG. 1C, some of the problems associated with the copper Damascene are captured and some typical thicknesses for the films involved are given. Firstly, the dishing and erosion of the copper is shown. Since copper is a soft material during CMP, the material loses planarity and the surface becomes bowed. This can make lithography of the subsequent steps complicated and can lead to a reduction in yield.
The side wall coverage with the barrier material is another major problem. This is because vacuum deposition, while effective on flat surfaces, can be problematic when it comes to high aspect ratio trenches and vias. Proper coverage of the sidewalls with the barrier material can cause the diffusion of the copper and can lead to serious problems, ultimately limiting the fabrication yield. Formation of voids within the copper is another major problem that arises during the electroplating process. Voids such as the one shown in FIG. 2 increase the electrical resistance of the trench and via and can lead to high current densities and heating. As is clear, these problems usually are in three dimensions. Prior art ellipsometry and reflectometry fail to characterize such yield limiting deviations. Therefore, a need clearly exists for characterizing these three-dimensional deviations in conjunction with film characterization and film thickness measurement.
In view of the foregoing, a need exists for an improved metrology and/or process monitoring system that overcomes the aforementioned obstacles and deficiencies of currently-available systems.